This invention relates to a method of synchronizing a xcexa3xcex94-modulator comprising a low pass filter and a quantizer in feedback arrangement, to an incoming single-bit bitstream, the method comprising the step of generating a correction signal from said incoming bitstream and adding said correction signal to at least one of the integrator stages of the low pass filter. Such method is known from a paper entitled: xe2x80x9cDigital Signal Processing in Direct Stream Digital Editing Systemxe2x80x9d by M. Noguchi et al presented to the 102nd AES Convention, held on Mar. 22-25, 1997 in Munich, Germany.
In current A/D and D/A conversion, xcexa3xcex94-modulators are frequently used because of the high linearity of their output signals compared to those of conventional PCM converters. The basic idea of the use of xcexa3xcex94-modulators is that the quantizer step can be made rather course, and that the loss in precision due to this approach is corrected for by oversampling. Oversampling itself is not enough to retain the quality mandatory for audio applications, and noise shaping is applied. The basic principle of noise shaping is to use a low pass filter in a feedback loop with the quantizer, in order to minimize the errors made in the quantizing step. For audio applications, an oversampling ratio of 64 is sufficient for high noise suppression, i.e. the clock frequency of the xcexa3xcex94-modulator is 64*44.1 kHz. Additionally, the high clock frequency provides a large bandwidth of the signal and removes the need for steep anti-aliasing filters.
For these reasons this single-bit format is adopted as the audio carrier format for the new generation of audio cd""s (Super Audio CD=SACD), in contrast to the multi-bit format which use many bits (e.g. 16 or 20) for the amplitude quantization and which run at sample frequencies marginally higher than the Nyquist frequency of the input signal. In the latter case, the input signal creates a unique sequence of bit-patterns (PCM). In the case of a xcexa3xcex94-modulator, on the contrary, only the average of the bit-pattern is unique; the sequence of the bits themselves is irrelevant. This implies that, when two identical xcexa3xcex94-modulators are fed with identical signals, but the initial states of the integrators are different, then the mere fact that these states are different results in two different bitstreams which never converge to identical bit-patterns.
As a result hereof, many signal processing routes (mixing, editing etc.) using single-bit bitstreams (often called DSD=Direct Stream Digital signals) do not work as with PCM, because signals are not bit-synchronised, i.e. the bits of the bitstreams are not simultaneously equal to each other. Another issue, arising from the same problem of the difficulty of synchronization, is in compression, where, in some way, the bitstream needs to be predicted. Without bit-synchronization, even a xcexa3xcex94-modulator with exactly the same input may produce a completely different output.
This synchronization problem could be circumvented by converting the single-bit signal to a low rate multi-bit (PCM) signal, subsequently carrying out the required signal processing and then reconverting the multi-bit signal to the required single-bit format. However, this would result in serious signal degradation, due to the steep anti-aliasing pre-filters which are required in these signal translations. In case the signal is converted to a high rate PCM-signal, then the stability of the reconversion xcexa3xcex94-modulator requires a pre-filter with a low cutoff frequency, which also results in significant loss of signal quality.
The above referenced paper discloses an editing system for single-bit bitstreams, in which a first bitstream is selected for outputting and thereafter a second bitstream. There between the output of a xcexa3xcex94-modulator is selected, which receives the faded-out first signal and the faded-in second signal. For bit-synchronizing the xcexa3xcex94-modulator to the second bitstream the offset between the second bitstream and the sum of the two faded signals is stored in an accumulator and, when the fading is completed, the stored offset is added little by little to the input of the xcexa3xcex94-modulator during an offset elimination time. It may be noted that adding the accumulated offset to the input of the xcexa3xcex94-modulator is equivalent to adding the offset to the first integrator stage of the low pass filter of the xcexa3xcex94-modulator. After the offset elimination time, the output is switched from the xcexa3xcex94-modulator to the second bitstream. The object of this synchronization procedure is to avoid clicks, which would otherwise occur at the switch-over from the requantized bitstream delivered by the xcexa3xcex94-modulator to the second bitstream.
However in this prior art system, when the audio content at the input of the xcexa3xcex94-modulator is small the input- and output-bitstreams of the xcexa3xcex94-modulator can easily be in anti-phase, so that the required bit-synchronization is not achieved. Moreover, the prior art system cannot be used when the relation of the incoming signal with the original bitstream is lost (e.g. after substantial signal processing). The present invention seeks to improve the bit-synchronization of a xcexa3xcex94-modulator to an incoming single-bit bitstream and therefore the method according to the invention is characterized by pre-filtering the incoming bitstream prior to application to the xcexa3xcex94-modulator and by generating the correction signal additionally from at least one of the pre-filtered input signal and the outgoing bitstream of the xcexa3xcex94-modulator. Therefore, by calculating the correction signal from both the incoming bitstream and at least one of the in- and output signals of the xcexa3xcex94-modulator, a much more reliable bit-synchronization of the xcexa3xcex94-modulator is obtained.
A first embodiment of the method according to the invention is characterized in that the correction signal is obtained by double integration of the difference between said incoming bitstream and one of the pre-filtered input signal and the outgoing bitstream of the xcexa3xcex94-modulator over a certain number of bits and dividing the result of said double integration by said certain number of bits. This method is easy to implement either in hardware or in software. However a disadvantage of this method is, that the synchronization is less accurate and that a large number of signal-bits (e.g. 2000) is required for the xcexa3xcex94-modulator to converge to the synchronized state. This disadvantage does not play a role in applications where enough data is available for synchronizing the xcexa3xcex94-modulator. An important example of such application is in signal editing systems. In such system, even xe2x80x9cfuturexe2x80x9d data can be used, because the output of an editor can be delayed by an arbitrary amount.
In contradistinction herewith, in applications where much less data are available for achieving the bit-synchronization of the xcexa3xcex94-modulator, such as in systems for compressing bitstream signals, the aforementioned, so called xe2x80x9cleast squaresxe2x80x9d method is not suitable and for those applications a second embodiment of the method of the invention is preferably used. This method is further characterized in that the correction signal is obtained by calculating the correction signal from the incoming bitstream and the pre-filtered input signal with an algorithm which is adapted to the structure of the low pass filter of the xcexa3xcex94-modulator.
This method of the invention may conveniently be used for compression and expansion of bitstream signals in order to reduce the amount of storage in case the bitstream signal has to be stored on a storage medium or the bandwidth or transmission time in case the signal has to be transmitted. In this case the method of the invention is further characterized in that, in a system for compression and expansion of single bit bitstream signals, the correction signal is transferred from the compression side to the expansion side.
The invention also relates to an arrangement for synchronizing a xcexa3xcex94-modulator which is characterized by a xcexa3xcex94-modulator, a pre-filter for pre-filtering the incoming bitstream and applying a pre-filtered input signal to the xcexa3xcex94-modulator, and a synchronizing unit for synchronizing the xcexa3xcex94-modulator to the incoming bitstream by applying a correction signal to at least one of the integrator states of the xcexa3xcex94-modulator, said synchronizing unit calculating the correction signal from the incoming bitstream and at least one of the pre-filtered input signal and the outgoing bitstream of the xcexa3xcex94-modulator.